There is a general demand for lower voltage, increased efficiency, high resolution and faster responses from power supplies. A generally recognized solution to this problem is the provision of multiple power supply devices on a single circuit board or more generally across multiple locations, for example, within a single computing device such as a server.
It is generally recognized that it is advantageous to have these multiple power supplies synchronized together to avoid problems such as beat frequencies and large output current ripple. To achieve synchronization between devices a number of different techniques have been developed.
These developed techniques include the approach of driving all the of the power supplies with a common clock. A problem with this approach is that it necessitates the provision of a relatively high speed clock signal possibly over a significant distance on a circuit which may be subject to noise and interference and/or indeed may generate same for other devices on the circuit board.
Another approach is to reduce the clock frequency of the master by a particular integer divisor to generate a sync signal and to multiply the sync signal by a corresponding integer multiple upon arrival at the slave side. A disadvantage of this approach is that in the event that there is no sync signal, e.g. where the master device malfunctions, then the slave circuit will not function. Another disadvantage is that an additional signal is required to phase align the master and slave PWM signals.
To solve this problem, it is known to employ a clock circuit within slave devices and to switch between the clock of the slave device and the clock signal generated from the master. This switch between the slave clock and the clock signal generated from the master may occur in response to the detection of the presence of the sync signal. The difficulty with this approach is that the transition between the two modes of operation is unpredictable and glitches such as the generation of multiple switching pulses in a given switching cycle from the slave PWM circuit may occur at the time of switchover. Another difficulty that can arise in these configurations is that if the sync signal from the master is lost or strays outside its normal operating range the slave circuit may fail to function either for a brief period or until the power is reset.